The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of Inx≥0.53Ga1-xAs/In0.52Al0.48As and Inx≥0.1Ga1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm2/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In0.85Ga0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (Lside) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH4)2S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al2O3/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×1012cm-2eV-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (Id,sat=1.14mA/mm), double peaked transconductance (gm=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (Ron=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of Id,sat (11×), gm (5.5×) and Ron (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (Lside) from 1μm down to 70nm improved Id,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In0.3Ga0.7Sb-channel (Id,sat=49.4mA/mm, gm=12.3mS/mm, Ron=31.7kΩ.μm) and In0.4Ga0.6Sb-channel (Id,sat=38mA/mm, gm=11.9mS/mm, Ron=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS

Fabrication and Characterization of Short Josephson Junctions with Stepped Ferromagnetic Barrier

We present novel low-T_c superconductor-insulator-ferromagnet-superconductor (SIFS) Josephson junctions with planar and stepped ferromagnetic interlayer. We optimized the fabrication process to set a step in the ferromagnetic layer thickness. Depending on the thickness of the ferromagnetic layer the ground state of the SIFS junction has a phase drop of either 0 or pi. So-called 0-pi Josephson junctions, in which 0 and pi ground states compete with each other, were obtained. These stepped junctions may have a double degenerate ground state, corresponding to a vortex of supercurrent circulating clock- or counterclockwise and creating a magnetic flux which carries a fraction of the magnetic flux quantum \Phi_0. Here, we limit the presentation to static properties of short junctions.Comment: modified version, small change

Plasma Processing of III-V Materials for Energy Efficient Electronics Applications

This paper reviews some recent activity at the James Watt Nanofabrication Centre in the University of Glasgow in the area of plasma processing for energy efficient compound semiconductor-based transistors. Atomic layer etching suitable for controllable recess etching in GaN power transistors will be discussed. In addition, plasma based surface passivation techniques will be reviewed for a variety of compound semiconductor materials ((100) and (110) oriented InGaAs and InGaSb)

Initial Investigation on the Impact of In Situ Hydrogen Plasma Exposure to the Interface Between Molecular Beam Epitaxially Grown P-Ga_0.7In_0.3Sb (100) and Thermal Atomic Layer Deposited (ALD) Al₂O₃

This work presents, to the best of the authors knowledge, the first experimental findings on the impact of in situ H<sub>2</sub> plasma exposure to the electrical properties of the interface between p-type Ga<sub>0.7</sub>In<sub>0.3</sub>Sb and atomic layer deposited Al<sub>2</sub>O<sub>3</sub>. The effects of trimethyl aluminium (TMA) exposure prior to Al<sub>2</sub>O<sub>3</sub> deposition, and of a post gate metal forming gas anneal (FGA) are also investigated. The control sample, which was subjected to an ex situ HCl clean prior to ALD only, demonstrated a capacitance modulation of 36.29 % before FGA. This degraded for samples exposed to the H<sub>2</sub> plasma for all plasma powers investigated. TMA exposure offered no improvement, and significantly increased the frequency dispersion in accumulation for all samples. A post gate metal FGA at 350 °C for 15 minutes was found to substantially improve the interface quality, with the capacitance modulation, frequency dispersion in accumulation and dC/dV improving by as much as 190 %, 91 %, and 170 % respectively

Electrical and physical characterization of the Al₂O₃/ <i>p</i>-GaSb interface for 1%, 5%, 10%, and 22% (NH₄)₂S surface treatments

In this work, the impact of ammonium sulfide ((NH&lt;sub&gt;4&lt;/sub&gt;)&lt;sub&gt;2&lt;/sub&gt;S) surface treatment on the electrical passivation of the Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt;/ &lt;i&gt;p&lt;/i&gt;-GaSb interface is studied for varying sulfide concentrations. Prior to atomic layer deposition of Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt;, GaSb surfaces were treated in 1%, 5%, 10%, and 22% (NH&lt;sub&gt;4&lt;/sub&gt;)&lt;sub&gt;2&lt;/sub&gt;S solutions for 10 min at 295 K. The smallest stretch-out and flatband voltage shifts coupled with the largest capacitance swing, as indicated by capacitance-voltage (&lt;i&gt;CV&lt;/i&gt;) measurements, were obtained for the 1% treatment. The resulting interface defect trap density (&lt;i&gt;D&lt;/i&gt;&lt;sub&gt;it&lt;/sub&gt;) distribution showed a minimum value of 4 x 10&lt;sup&gt;12&lt;/sup&gt; cm&lt;sup&gt;-2&lt;/sup&gt;eV&lt;sup&gt;-1&lt;/sup&gt; at &lt;i&gt;E&lt;/i&gt;&lt;sub&gt;v&lt;/sub&gt; + 0.27 eV. Transmission electron microscopy and atomic force microscopy examination revealed the formation of interfacial layers and increased roughness at the Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt;/ &lt;i&gt;p&lt;/i&gt;-GaSb interface of samples treated with 10% and 22% (NH&lt;sub&gt;4&lt;/sub&gt;)&lt;sub&gt;2&lt;/sub&gt;S. In combination, these effects degrade the interface quality as reflected in the &lt;i&gt;CV&lt;/i&gt; characteristics

(Invited) towards a vertical and damage free post-etch InGaAs fin profile: dry etch processing, sidewall damage assessment and mitigation options

Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins

The impact of forming gas annealing on the electrical characteristics of sulfur passivated Al2O3/In0.53Ga0.47As (110) metal-oxide-semiconductor capacitors

This study reports the impact of forming gas annealing (FGA) on the electrical characteristics of sulfur passivated, atomic layer deposited Al2O3 gate dielectrics deposited on (110) oriented n- and p-doped In0.53Ga0.47 As layers metal-oxide-semiconductor capacitors (MOSCAPs). In combination, these approaches enable significant Fermi level movement through the bandgap of both n- and p-doped In0.53Ga0.47 As (110) MOSCAPs. A midgap interface trap density (Dit) value in the range 0.87−1.8×1012 cm−2eV−10.87−1.8×1012 cm−2eV−1 is observed from the samples studied. Close to the conduction band edge, a Dit value of 3.1×1011 cm−2eV−13.1×1011 cm−2eV−1 is obtained. These data indicate the combination of sulfur pre-treatment and FGA is advantageous in passivating trap states in the upper half of the bandgap of (110) oriented In0.53Ga0.47 As. This is further demonstrated by a reduction in border trap density in the n-type In0.53Ga0.47 As (110) MOSCAPs from 1.8×1012 cm−21.8×1012 cm−2 to 5.3×1011 cm−25.3×1011 cm−2 as a result of the FGA process. This is in contrast to the observed increase in border trap density after FGA from 7.3×1011 cm−27.3×1011 cm−2 to 1.4×1012 cm−21.4×1012 cm−2 in p-type In0.53Ga0.47 As (110) MOSCAPs, which suggest FGA is not as effective in passsivating states close to the valence band edge

(Invited) The inversion behaviour of narrow band gap MOS systems: experimental observations, physics based simulations and applications

Impedance spectroscopy of the metal-oxide semiconductor (MOS) system has played a central role in the development of silicon-based complementary MOS (CMOS) technology over the past 50 years [1, 2]. With current research interest into alternative semiconductor channels to silicon for MOSFET and tunnel FET technologies, the measurement and interpretation of the overall impedance of the MOS structure requires detailed analysis to separate and quantify the contribution of interface states, and near interface traps (border traps), on the capacitance and conductance response, and to separate the contribution of these electrically active defect states from the ac response of minority carriers in the case of genuine inversion of the semiconductor/dielectric interface

Material for III-V Nanowires

No abstract available

Initial Investigation on the Impact of In Situ Hydrogen Plasma Exposure to the Interface Between Molecular Beam Epitaxially Grown P-Ga_0.7In_0.3Sb (100) and Thermal Atomic Layer Deposited (ALD) Al₂O₃

This work presents, to the best of the authors knowledge, the first experimental findings on the impact of in situ H&lt;sub&gt;2&lt;/sub&gt; plasma exposure to the electrical properties of the interface between p-type Ga&lt;sub&gt;0.7&lt;/sub&gt;In&lt;sub&gt;0.3&lt;/sub&gt;Sb and atomic layer deposited Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt;. The effects of trimethyl aluminium (TMA) exposure prior to Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt; deposition, and of a post gate metal forming gas anneal (FGA) are also investigated. The control sample, which was subjected to an ex situ HCl clean prior to ALD only, demonstrated a capacitance modulation of 36.29 % before FGA. This degraded for samples exposed to the H&lt;sub&gt;2&lt;/sub&gt; plasma for all plasma powers investigated. TMA exposure offered no improvement, and significantly increased the frequency dispersion in accumulation for all samples. A post gate metal FGA at 350 °C for 15 minutes was found to substantially improve the interface quality, with the capacitance modulation, frequency dispersion in accumulation and dC/dV improving by as much as 190 %, 91 %, and 170 % respectively